Digital data processors to which this invention is applicable employ a two-level memory subsystem. There are level one memories which cache and a level two memory which includes directly addressable RAM, cache or both. The RAM of the level two memory can be cached in level one All cache allocates (level one data, level one instruction and level two) are processed by a level two controller to direct memory access (DMA) controller with interfaces with the peripheral which supplied the data. The level two cache line size is preferably 128 bytes. Because this data is to be brought from an external peripheral, this data transfer can take a long time. The number of cycles needed to fetch this data affects the total amount of time that the level two controller is busy. This affects the performance of the level two controller. The latency of this fetch and the order in which data returns directly affects the stalls visible to the CPU and the performance of the system.